dc.contributor.author | Grabinski, W. | |
dc.contributor.author | Pavanello, M. | |
dc.contributor.author | Souza, M. d. | |
dc.contributor.author | Tomaszewski, D. | |
dc.contributor.author | Malesinska, J. | |
dc.contributor.author | Gluszko, G. | |
dc.contributor.author | Bucher, M. | |
dc.contributor.author | Makris, N. | |
dc.contributor.author | Nikolaou, A. | |
dc.contributor.author | Abo-Elhadid, A. | |
dc.contributor.author | Mierzwinski, M. | |
dc.contributor.author | Lemaitre, L. | |
dc.contributor.author | Brinson, M. | |
dc.contributor.author | Lallement, C. | |
dc.contributor.author | Sallese, J. | |
dc.contributor.author | Yoshitomi, S. | |
dc.contributor.author | Malisse, P. | |
dc.contributor.author | Oguey, H. | |
dc.contributor.author | Cserveny, S. | |
dc.contributor.author | Enz, C. | |
dc.contributor.author | Krummenacher, F. | |
dc.contributor.author | Vittoz, E. | |
dc.date.accessioned | 2021-12-09T14:03:59Z | |
dc.date.available | 2021-12-09T14:03:59Z | |
dc.date.issued | 2019 | |
dc.identifier.citation | ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), pp. 190-193 | |
dc.identifier.uri | https://yoda.csem.ch/handle/20.500.12839/343 | |
dc.description.abstract | The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice. | |
dc.subject | EKV2.6 model;compact/SPICE model;Verilog-A | |
dc.title | FOSS EKV2.6 Verilog-A Compact MOSFET Model | |
dc.type | Proceedings Article | |
dc.type.csemdivisions | Div-M | |
dc.type.csemresearchareas | ASICs for the Edge | |
dc.identifier.doi | https://doi.org/10.1109/ESSDERC.2019.8901822 | |