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dc.contributor.authorPons, M.
dc.contributor.authorThanh-Chau Le, C.
dc.contributor.authorArm, C.
dc.contributor.authorSeverac, D.
dc.date.accessioned2021-12-09T12:46:49Z
dc.date.available2021-12-09T12:46:49Z
dc.date.issued2015
dc.identifier.citationSOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
dc.identifier.urihttps://yoda.csem.ch/handle/20.500.12839/49
dc.description.abstractA 1kb 180 nm single-side read 6T sub-threshold SRAM has been designed focusing on manufacturability, integrated and measured satisfactorily. Silicon measurements show 3.1 nA total current, 2.4 nA leakage, at 530 Hz for a minimum operating voltage of 0.27 V with no bit errors. The area of the block is 22'350 µm2.
dc.subjectCMOS, IC, SRAM, sub-threshold, ultra-low-power
dc.titleA 1kb single-side read 6T sub-threshold SRAM in 180 nm with 530 Hz frequency 3.1 nA total current and 2.4 nA leakage at 0.27 V
dc.typeProceedings Article
dc.type.csemdivisionsDiv-M
dc.type.csemresearchareasASICs for the Edge
dc.identifier.doihttps://dx.doi.org/10.1109/S3S.2015.7333550


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