Browsing CSEM Archive by Research Areas "ASICs for the Edge"

A 0.5 V 2.5 uW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS

Pons, M.; MÃ¼ller, C. T.; Ruffieux, D.; Nagel, J.; Emery, S.; Burg, A.; Tanahashi, S.; Tanaka, Y.; Takeuchi, A. (2019)

Microcontroller systems operating at low supply voltage in near or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power ...

A 1kb single-side read 6T sub-threshold SRAM in 180 nm with 530 Hz frequency 3.1 nA total current and 2.4 nA leakage at 0.27 V

Pons, M.; Thanh-Chau Le, C.; Arm, C.; Severac, D. (2015)

A 1kb 180 nm single-side read 6T sub-threshold SRAM has been designed focusing on manufacturability, integrated and measured satisfactorily. Silicon measurements show 3.1 nA total current, 2.4 nA leakage, at 530 Hz for a ...

A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge

Jokic, P.; Azarkhish, E.; Cattenoz, R.; Türetken, E.; Benini, L.; Emery, S. (2021-06)

Battery-Less Face Recognition at the Extreme Edge

Jokic, P.; Emery, S.; Benini, L. (2021-06)

Benchmarking Neuromorphic Computing for Inference

Narduzzi, Simon; Mateu, Loreto; Jokic, Petar; Azarkhish, Erfan; Dunbar, L. Andrea (2022-06)

In the last decade, there has been significant progress in the IoT domain due to the advances in the accuracy of neural networks and the industrialization of efficient neural network accelerator ASICs. However, intelligent ...

Comparison Of Capacitive DAC Architectures for Power and Area Efficient SAR ADC Designs

Ahuja, A.; Badami, K.; Barbelenet, C.; Emery, S. (2021-05)

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Jokic, Petar, Dr.; Azarkhish, Erfan, Dr.; Bonetti, Andrea, Dr.; Pons, Marc, Dr.; Emery, Stephane, Dr.; Benini, Luca, Prof. Dr. (2022-09)

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that combines high computational throughput with low power consumption. Driven by the rapid evolution of network architectures ...

Deploying a Convolutional Neural Network on Edge MCU and Neuromorphic Hardware Platforms

Narduzzi, Simon; Favre, Dorvan; Nuria, Pazos; Dunbar, L. Andrea (2022-06)

The rapid development of embedded technologies in recent decades has led to the advent of dedicated inference platforms for deep learning. However, unlike development libraries for the algorithms, hardware deployment is ...

Efficient Neural Vision Systems Based on Convolutional Image Acquisition

Pad, Pedram; Narduzzi, Simon; Kündig, Clément; Türetken, Engin; Bigdeli, Siavash A.; Dunbar, L. Andrea (2020-06-14)

Despite the substantial progress made in deep learning in recent years, advanced approaches remain computationally intensive. The trade-off between accuracy and computation time and energy limits their use in real-time ...

Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-ÂµW to 4.32mW

Deng, J.; Nagel, J.; Zahnd, L.; Pons, M.; Ruffieux, D.; Arm, C.; Persechini, P.; Emery, S. (2019)

We describe a SoC achieving zero-net-energy operation by using energy harvesting and sub-threshold design. It consists of a microcontroller for data acquisition, data processing, and communication and an energy harvester ...

Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities

Valencia, F.; Polian, I.; Regazzoni, F. (2021-09)

FOSS EKV2.6 Verilog-A Compact MOSFET Model

Grabinski, W.; Pavanello, M.; Souza, M. d.; Tomaszewski, D.; Malesinska, J.; Gluszko, G.; Bucher, M.; Makris, N.; Nikolaou, A.; Abo-Elhadid, A.; Mierzwinski, M.; Lemaitre, L.; Brinson, M.; Lallement, C.; Sallese, J.; Yoshitomi, S.; Malisse, P.; Oguey, H.; Cserveny, S.; Enz, C.; Krummenacher, F.; Vittoz, E. (2019)

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software ...