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dc.contributor.authorValencia, F.
dc.contributor.authorPolian, I.
dc.contributor.authorRegazzoni, F.
dc.date.accessioned2022-02-21T13:57:38Z
dc.date.available2022-02-21T13:57:38Z
dc.date.issued2021-09
dc.identifier.citation2021 24th Euromicro Conference on Digital System Design (DSD), 2021, pp. 385-388en_US
dc.identifier.urihttps://yoda.csem.ch/handle/20.500.12839/997
dc.titleExtending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilitiesen_US
dc.typeProceedingsen_US
dc.type.csemdivisionsDiv-Men_US
dc.type.csemresearchareasASICs for the Edgeen_US
dc.identifier.doi10.1109/DSD53832.2021.00065


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