IP library for the acceleration of edge AI/ML
Abstract
A library with a wide selection of hardware IPs for the design
of modular and flexible SoCs that enable end-to-end inference
on miniaturized systems. Available IP categories include ML
accelerators, dedicated memory systems, the RISC-V based
32-bit processor core icyflex-V, and peripherals.
Publication Reference
CSEM technical factsheet M12.23
Year
2023-12