IP library for the acceleration of edge AI/ML

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dc.contributor.authorCSEM, ASICs for the edge
dc.date.accessioned2024-04-04T13:34:08Z
dc.date.available2024-04-04T13:34:08Z
dc.date.issued2023-12
dc.description.abstractA library with a wide selection of hardware IPs for the design of modular and flexible SoCs that enable end-to-end inference on miniaturized systems. Available IP categories include ML accelerators, dedicated memory systems, the RISC-V based 32-bit processor core icyflex-V, and peripherals.
dc.identifier.citationCSEM technical factsheet M12.23
dc.identifier.urihttps://hdl.handle.net/20.500.12839/1376
dc.language.isoen
dc.rightsCC0 1.0 Universal*
dc.rights.urihttp://creativecommons.org/publicdomain/zero/1.0/*
dc.titleIP library for the acceleration of edge AI/ML
dc.typeTechnical Factsheet
dc.type.csemdivisionsBU-M
dc.type.csemresearchareasASICs for the Edge
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