A DC-Coupled Neural Recording Analog Front-End with Bi-Level Bulk Modulation-Based EDO Compensation in 40nm Bulk CMOS
| dc.contributor.author | Diez-Clos, Arnau | |
| dc.contributor.author | Huang, Xiaohua | |
| dc.contributor.author | Monna, Bert | |
| dc.contributor.author | Muratore, Dante G. | |
| dc.date.accessioned | 2025-12-01T13:20:17Z | |
| dc.date.available | 2025-12-01T13:20:17Z | |
| dc.date.issued | 2025 | |
| dc.description.abstract | This paper presents a compact, low-power analog front-end (AFE) for high-density micro-electrocorticography (μECoG) recordings. The AFE integrates a DC-coupled, chopper-stabilized low-noise boxcar sampler, a passive switched-capacitor low-pass filter, and a 10-bit single-slope analog-to-digital converter (ADC). The boxcar sampler minimizes noise folding, enhances anti-aliasing and reduces chopping ripple. To prevent AFE saturation, a novel electrode DC offset (EDO) compensation loop is introduced. It features an embedded digital-to-analog converter (DAC) by modulating the bulk terminals of the input transistors, and a bi-level compensation scheme, thereby eliminating the requirements for high-resolution digital low-pass filters and explicit DACs typically used in traditional DC servo loops. Simulation results in 40nm bulk CMOS show an input-referred noise of 1.69 μVrms over a 1-500 Hz bandwidth, an EDO compensation range of 110 mVpp, with a power consumption of 2.28 μW and an estimated area of 0.0028 mm2 per channel | |
| dc.identifier.citation | A. Diez-Clos, X. Huang, B. Monna and D. G. Muratore, "A DC-Coupled Neural Recording Analog Front-End with Bi-Level Bulk Modulation-Based EDO Compensation in 40nm Bulk CMOS," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1-5, doi: 10.1109/ISCAS56072.2025.11044232. keywords: {Electrodes;Technological innovation;Simulation;Noise;Low-pass filters;Channel estimation;Switches;Recording;Transistors;Servomotors;Neural recording;analog front-end (AFE);micro-electrocorticography (μECoG);chopper stabilization;bilevel compensation (BLC);bulk modulation;electrode DC offset (EDO)}, | |
| dc.identifier.doi | 10.1109/ISCAS56072.2025.11044232 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12839/1881 | |
| dc.language.iso | en | |
| dc.title | A DC-Coupled Neural Recording Analog Front-End with Bi-Level Bulk Modulation-Based EDO Compensation in 40nm Bulk CMOS | |
| dc.type | Conference | |
| dc.type.csemdivisions | BU-M | |
| dc.type.csemresearchareas | Other | |
| dc.type.csemresearchareas | ASICs for the Edge |