A 20 Channel EMG SoC with an Integrated 32b RISC Core for Real-Time Wireless Prosthetic Control

Simple item page
dc.contributor.authorSole, M. P.
dc.contributor.authorBadami, K.
dc.contributor.authorDeng, J.
dc.contributor.authorMavrogordatos, T.
dc.contributor.authorAzarkhish, E.
dc.contributor.authorZahnd, L.
dc.contributor.authorCosentino, C.
dc.contributor.authorAugustyniak, M.
dc.contributor.authorZha, Y.
dc.contributor.authorBischof, A.
dc.contributor.authorBergamini, L.
dc.contributor.authorDallemagne, P.
dc.contributor.authorEmery, S.
dc.date.accessioned2021-12-09T14:03:59Z
dc.date.available2021-12-09T14:03:59Z
dc.date.issued2019
dc.description.abstractThis work introduces a highly integrated and a power-efficient SoC with 20 EMG sensing channels, a 32b RISC core with a host of peripherals and a companion RF transceiver chip in the 55 nm CMOS technology to enable real-time Osseo-integrated prosthesis control and is aimed at recovery of hand function after amputation. The EMG processing channels include temperature compensated pseudo-resistors in highly programmable gain stages, a 4th order Chebyshev low-pass filter with enhanced linearity and 12b SAR ADC operating in the programmable range of 1.2MS/s to 125kS/s for multichannel EMG signal digitization. The digital back-end includes an EMG pre-processing accelerator and a 32b RISC processor that optimizes the power-consumption of the companion RF transceiver to improve the power-efficiency of the the prosthesis control system.
dc.identifier.citationESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), pp. 73-76
dc.identifier.doihttps://doi.org/10.1109/ESSCIRC.2019.8902881
dc.identifier.urihttps://hdl.handle.net/20.500.12839/342
dc.titleA 20 Channel EMG SoC with an Integrated 32b RISC Core for Real-Time Wireless Prosthetic Control
dc.typeProceedings Article
dc.type.csemdivisionsBU-M
dc.type.csemresearchareasIoT & Vision
Files
Collections
Research Publications