Low-power RISC-V subsystems
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Author
CSEM, ASICs for the edge
DOI
Abstract
CSEM has a long experience designing RISC-V system-onchips
based on the open instruction set architecture (ISA)
defined by the RISC-V foundation which is supported by
standard state-of-the-art development tools (both opensource
and proprietary).
Many core options are possible and easily interchangeable,
ranging from proprietary (icyflex-V) to open-source (e.g.
OpenHW core-v) covering needs from ultra-low power microcontrollers
(well suited for IoT, wearables and mixed signal
applications) to higher-performance systems for example for
vision applications.
Publication Reference
CSEM technical factsheet M12.23
Year
2023-12