Fibonacci machine-learning (ML) system-on-chip (SoC)
| dc.contributor.author | CSEM, ASICs for the edge | |
| dc.date.accessioned | 2024-03-21T15:46:35Z | |
| dc.date.available | 2024-03-21T15:46:35Z | |
| dc.date.issued | 2023-12 | |
| dc.description.abstract | Hierarchical scalability is the foundation principle of CSEM’s Fibonacci machine-learning (ML) system-on-chip (SoC). Like the Fibonacci number series, combining each element by the sum of the previous ones, the SoC can dynamically increase its computational performance by adding accelerator resources based on the application’s needs. I | |
| dc.identifier.citation | CSEM technical factsheet M12.23 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12839/1369 | |
| dc.title | Fibonacci machine-learning (ML) system-on-chip (SoC) | |
| dc.type | Technical Factsheet | |
| dc.type.csemdivisions | BU-M | |
| dc.type.csemresearchareas | ASICs for the Edge |