A Low-jitter Reference-less Clock and Data Recovery (CDR) with Low Phase-noise Multi-clock Generation

dc.contributor.authorSalazar, Camilo
dc.contributor.authorChicco, Francesco
dc.contributor.authorDissanayake, Anjana
dc.contributor.authorVouilloz, Alexandre
dc.contributor.authorRuffieux, David
dc.contributor.authorStanarevic, Srdjan
dc.contributor.authorRavanilla, Renil
dc.contributor.authorGerber, Nicola
dc.contributor.authorScolari, Nicola
dc.contributor.authorVon Allmen, Laurent
dc.contributor.authorBen Salah, Mohammed Ismail
dc.contributor.authorDal Fabbro, Paulo Augusto
dc.date.accessioned2024-06-03T13:28:16Z
dc.date.available2024-06-03T13:28:16Z
dc.date.issued2023
dc.identifier.citationCSEM Scientific and Technical Report 2023, p. 28
dc.identifier.urihttps://hdl.handle.net/20.500.12839/1409
dc.language.isoen
dc.titleA Low-jitter Reference-less Clock and Data Recovery (CDR) with Low Phase-noise Multi-clock Generation
dc.typeCSEM Report
dc.type.csemdivisionsBU-M
dc.type.csemresearchareasASICs for the Edge
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