A 32-kHz Bandwidth Reconfigurable Delta Sigma ADC providing up to 13 ENOB
Abstract
A solution including an input buffer with programmable
gain, followed by a Delta Sigma Modulator (DSM) and a
Decimation filter is provided. Additionally, the voltage
reference buffers, the current generation and DC bias
generators are integrated within this solution.
Publication Reference
CSEM technical factsheet M11.21
Year
2021-11