FOSS EKV2.6 Verilog-A Compact MOSFET Model

dc.contributor.authorGrabinski, W.
dc.contributor.authorPavanello, M.
dc.contributor.authorSouza, M. d.
dc.contributor.authorTomaszewski, D.
dc.contributor.authorMalesinska, J.
dc.contributor.authorGluszko, G.
dc.contributor.authorBucher, M.
dc.contributor.authorMakris, N.
dc.contributor.authorNikolaou, A.
dc.contributor.authorAbo-Elhadid, A.
dc.contributor.authorMierzwinski, M.
dc.contributor.authorLemaitre, L.
dc.contributor.authorBrinson, M.
dc.contributor.authorLallement, C.
dc.contributor.authorSallese, J.
dc.contributor.authorYoshitomi, S.
dc.contributor.authorMalisse, P.
dc.contributor.authorOguey, H.
dc.contributor.authorCserveny, S.
dc.contributor.authorEnz, C.
dc.contributor.authorKrummenacher, F.
dc.contributor.authorVittoz, E.
dc.description.abstractThe EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.
dc.identifier.citationESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), pp. 190-193
dc.subjectEKV2.6 model;compact/SPICE model;Verilog-A
dc.titleFOSS EKV2.6 Verilog-A Compact MOSFET Model
dc.typeProceedings Article
dc.type.csemresearchareasASICs for the Edge