A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge

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dc.contributor.authorJokic, P.
dc.contributor.authorAzarkhish, E.
dc.contributor.authorCattenoz, R.
dc.contributor.authorTüretken, E.
dc.contributor.authorBenini, L.
dc.contributor.authorEmery, S.
dc.date.accessioned2021-12-15T19:07:50Z
dc.date.available2021-12-15T19:07:50Z
dc.date.issued2021-06
dc.identifier.citation2021 Symposium on VLSI Circuits, 2021, pp. 1-2
dc.identifier.doihttps://doi.org/10.23919/VLSICircuits52068.2021.9492401
dc.identifier.urihttps://hdl.handle.net/20.500.12839/502
dc.titleA Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge
dc.typeProceedings Article
dc.type.csemdivisionsBU-M
dc.type.csemresearchareasASICs for the Edge
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