A 0.5 V 2.5 uW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS

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dc.contributor.authorPons, M.
dc.contributor.authorMüller, C. T.
dc.contributor.authorRuffieux, D.
dc.contributor.authorNagel, J.
dc.contributor.authorEmery, S.
dc.contributor.authorBurg, A.
dc.contributor.authorTanahashi, S.
dc.contributor.authorTanaka, Y.
dc.contributor.authorTakeuchi, A.
dc.date.accessioned2021-12-09T14:03:28Z
dc.date.available2021-12-09T14:03:28Z
dc.date.issued2019
dc.description.abstractMicrocontroller systems operating at low supply voltage in near or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. We show how to overcome these effects for the core and memory by exploiting the strong body factor of deeply depleted channel CMOS at 0.5 V, compensating frequency over PVT to ±6%, achieving 30x frequency and 20x leakage scaling in a 2.56 uW/MHz 32 bit RISC Core with 3.13 nW/kB 2.5 uW/MHz SRAM. Frequency-leakage configurability in core and SRAM through adaptive body bias at fixed supply voltage is implemented using a novel automatic analog-assisted ION-controlled approach.
dc.identifier.citation2019 IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4
dc.identifier.doihttps://doi.org/10.1109/CICC.2019.8780199
dc.identifier.urihttps://hdl.handle.net/20.500.12839/341
dc.subjectLow Power;Microcontroller;SoC;PVT Compensation;Body Bias;Adaptive Body Bias
dc.titleA 0.5 V 2.5 uW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS
dc.typeProceedings Article
dc.type.csemdivisionsBU-M
dc.type.csemresearchareasASICs for the Edge
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