A high-PSRR and low-noise CMOS-based reference with barrel shifting and notch filtering
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Author
Miotello, Enrico
Sukumaran, Amrith
Zhang, Chun-Min
Caruso, Francesco
Cruz, Paula Blanca
Emery, Stéphane
DOI
10.1109/ISCAS56072.2025.11043911
Abstract
This work presents a fully integrated, low-noise, CMOS reference generator capable of operating at supply voltages from 0.7 V up to 1.5 V. A 3-phase barrel shifting technique is proposed to upconvert the flicker noise, achieving an integrated noise of 19.7 μVrms over a 10 kHz bandwidth undertypical conditions (0.7 V, 27 °C), without needing bulky off-chip filters. The untrimmed reference voltage from post-layout simulations exhibits an average temperaturedrift of 30 ppm/°C across the full temperature range of -40 °C to 125 °C. A 2-stage switched-capacitor notch filter that is proposed, brings a 60-fold reduction in the upconverted voltage ripple, and a 40 dB reduction in thermal noise at 10kHz while resulting in an exceptional Power Supply Rejection Ratio (PSRR) of -95 dB at 50 Hz. The circuit is implemented in a 22-nm FDSOI process, occupying an area of only 0.01 mm2 while consuming a power of 288 nW at the typical condition.
Publication Reference
2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, UK, pp. 1-5
Year
2025
Sponsors
This work has received funding from the Swiss State Secretariat for Education, Research, and Innovation (SERI) under the SwissChips initiative